The work will involve development
and qualification of IC Validator DRC/ERC/LVS/Fill runsets ( rule deck files)
for various cutting edge technologies. You may also be involved in various
automation activity to qualify the IC Validator runset.
Person should have B. Tech/M.Tech/MS degree in Electronics/VLSI domain. Should have understanding and exposure to transistor CMOS layouts. Proficient with Perl/Tcl, Unix, HDL
(Verilog/VHDL) and a strong understanding of ASIC design flow, VLSI, and/or CAD
engineering. Knowledge of competitive EDA tool products like
Calibre/Assura/Quartz and product knowledge in any of the areas ofwriting
foundry decks ( DRC/LVS/ERC/DFM), solving LVS issues, knowledge of foundry
processes, understanding of cutting edge DFM requirements are highly desired.
The internship period is one year.