Synopsys Hiring for fresher 2014 Passout | Electronics/ Electrical
|INDIA – Bangalore|
Job description for Intern
The selected intern candidate will be part of the IP verification/ VIP team in Solutions Group, Synopsys , India and be based at Bangalore.
The focus area of activities would be Verification/ VIP/ Test Environment development in System Verilog/ Vera in a VMM environment in one of the following domain :USB3/USB2/Ethernet/MIPI
The intern will be taken through hands-on training in Verification methodologies such as VMM and in the respective domain.
Subsequent to training, the nature of work would be on the following lines:
Understanding product architecture for VIP or Test environment, coding in one of the HVL such as System Verilog, Verification of the blocks that are coded, understanding and implementing functional coverage infrastructure. It will involve closely working as part of the product development team.
Candidates with good problem solving skills and kknowledge of HDL such as Verilog with strong concepts in OOPs and C++. Exposure to HVL Languages such as SystemVerilog/Vera/SpecmanE is highly preferable. Aptitude to work in VLSI Verification domain is a must and only those who are willing to put it extra effort and take up technical challenges need apply .
The candidate must have completed Bachelors degree in electronics/ Electrical engg with minimum 70% or 7.0 CGPA.
Partial or full completion of MS/MTech is preferable with overall grades of 7.0 or above.
Duration of internship:
The duration of internship will be for 6 months extendible to one year based on performance. Longer duration will be considered for candidates who are doing the internship as part of the academic requirements.
Process of selection
Process of selection will be through a written test followed by interview.